In recent years, techniques for reducing interconnect resistance and interline capacitance have been developed to achieve higher performance of semiconductor devices. As one of the techniques for reducing interconnect resistance, known is copper metallization using a damascene process. A so-called dual damascene process, in which interconnections and via plugs are simultaneously formed, is particularly effective in reducing interconnect resistance.
Since interconnections are formed in interlayer dielectrics, low-k interlayer dielectrics are used to reduce interconnect resistance. For example, a low-k interlayer dielectric with a relative dielectric constant of 2.5 or less has been desired. Specifically, a dual damascene process using a film of a porous material has been developed.
A porous film has such characteristics that the properties thereof are changed through a dry etching process and that the etching rate thereof is higher than that of a non-porous film. Etching control on porous films is very difficult. When an interlayer dielectric consisting of a porous film is used in a dual damascene process, in a step of etching to form the shapes of interconnections, portions of the porous film located at the bottoms of the interconnections are particularly changed in properties. Unnecessary excessive etching of the porous film leads to difficulty in forming multilayer interconnections having desired properties.
In ‘Copper Dual Damascene Interconnects with Low-K (Keff<3.0) Dielectrics Using FLARE and Organo-Silicate Hard Mask’ International Electron Devices Meeting (IEDM) 1999, pp. 623, described is a method in which an etching stopper film is provided between a porous film where via plugs are located and a porous film where interconnections are located. This etching stopper film is a non-porous film which has a high etching selectivity ratio relative to the porous films. The etching stopper film facilitates the etching control on the porous films and prevents changes in properties of the porous films. The etching stopper film protects the porous film located at the bottoms of the interconnections from being etched more than needed. For the etching stopper film, SiCH film, SiCN film, or an organic film is used.
Each of the above-mentioned films is similar, in composition, to a resist mask and a passivation film (protective film) formed on surfaces of interconnections (e.g., embedded interconnections) immediately below upper-layer interconnections of dual damascene structures. In steps of removing the resist mask and the passivation film at the bottoms of via holes, the etching stopper film is also etched. The porous film is exposed at the bottoms of the interconnections, and it becomes difficult to form via plugs to designed dimensions.
The etching stopper film is made thick so that the etching stopper film is left at a sufficient thickness even after the steps of removing the respective members. SiCH film, SiCN film, or an organic film used for the etching stopper film has a higher dielectric constant than that of a porous film. The use of a thick etching stopper film will lead to an increase in interline capacitance.